Many computer systems include a plurality of processing units, e.g., master processors, that simultaneously interact with shared resources, such as I/0 devices, slave processors and memory devices. The master processors of these systems are typically coupled to the various resources via a single address bus and a single data bus. Signals to/from the respective master processors must be sent from/to the respective resource devices over one of these buses.
There are three important parameters that must be considered when defining a bus: bandwidth, latency and cost.
Bandwidth is a measure of the quantity of data that can be transferred over the bus per second. Bandwidth is important because the data bus connecting the memory devices to the master processors can create a "bottleneck" through which all memory transactions must pass; thus, a large-bandwidth data bus is important to the overall speed of the computer system.
Latency represents the time it takes to transfer data between memory and a processor. A great deal of complexity can be added to a system to improve bandwidth and latency; however, this added complexity increases the cost of the system. A goal of the bus designer is to maximize bandwidth and minimize latency for the least possible cost. To achieve this goal, a protocol is required for accessing the address bus when more than one of the master processors "desires" to conduct a transaction with one of the resources, e.g., a read or write to or from memory. In theory an infinite variety of such protocols is possible, however it is desirable that the protocol facilitate a simplified bus design by standardizing all transactions. It is further desirable that the protocol not require the memory devices to be complex, or "smart." The present invention achieves these goals.